1. Field of the Invention
The invention relates to a combination of a test circuit and a ferroelectric memory.
U.S. Pat. No. 5,254,482 discloses a circuit configuration that includes a ferroelectric memory and a test circuit.
Integrated ferroelectric semiconductor memory circuits (Ferro-Electric Random Access Memories, FeRAMs) can be constructed in a manner similar to conventional dynamic memories (Dynamic Random Access Memories, DRAMs), but differ from the latter through the nonvolatility of the memory content and through differently configured aging phenomena. Tests of the nonvolatility (retention) and of the aging (e.g. fatigue, imprint, disturb, . . . ) therefore require new methods in comparison with DRAM tests. Typical DRAM tests include a digital evaluation of the memory content. What is advantageous for the statistical assessment and extrapolation of the decrease in the memory content through stress (for example in the case of electrical or mechanical loading, storage, thermal treatment, irradiation, chemical reactions, . . . ) is, however, an analog evaluation of the memory content through the measurement of analog values of the stored potential. In other words, the analog measurement of bit line signals can already reveal slight stress-induced changes in the potential stored in the cell. This results in substantially more accurate knowledge of the stress influence on the reliability.
In the case of ferroelectric memory components in development, the path taken heretofore has been to use a special test mode to indirectly carry out an analog evaluation of the potential stored in the memory cell. As in the case of a DRAM, a customary sense amplifier was used here to compare the bit line signal to be evaluated with a reference signal on a reference bit line. The potential of the reference signal could be adjusted externally. By progressively altering the externally adjustable reference voltage and comparing the two bit line signals with the aid of the sense amplifier, it was possible to obtain a quasi analog information item. However, most of the types of stress could not be evaluated quantitatively using this test method, since the information about the stress influence is lost as early as after the first of the many evaluation cycles required, on account of the destructive read operation of an FeRAM.
Analog information obtained in a test of customary DRAMs has a substantially smaller information content in comparison with a stress test to be carried out in the case of an FeRAM.
In the case of the known combination of a ferroelectric memory component with a test circuitxe2x80x94described in U.S. Pat. No. 5,254,482xe2x80x94the latter is integrated as a ferroelectric capacitor at the edge of a chip having ferroelectric memory components, and is connected on the one hand to a line that feeds voltage to the ferroelectric memory cells, and on the other hand to a test pad. In this way, the ferroelectric capacitor serves as a dummy memory cell which supplies analog output signals which can be used for extrapolating the aging and fatigue characteristic values of other ferroelectric components in the ferroelectric memory component. In other words, in the case of the known circuit combination, the test circuit does not acquire the genuine signal valuesxe2x80x94occurring on the bit lines of the ferroelectric memory componentxe2x80x94from the ferroelectric memory cells, but instead the signal values that are read out from the ferroelectric capacitor serving as a dummy cell.
It is accordingly an object of the invention to provide a circuit configuration which overcomes the above-mentioned disadvantages of the heretofore-known circuit configurations of this general type and which has a cost-effective test circuit for the analog measurement of bit line signals of ferroelectric memory cells with the aid of which the content of ferroelectric memory cells can be read out quantitatively via the potentials on the bit lines and which allows reliable and time-saving evaluation of all stress influences.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, including:
a ferroelectric memory component having a plurality of ferroelectric memory cells, bit lines and sense amplifiers connected to the bit lines;
a test circuit including a plurality of analog amplifiers each connected, on an input side thereof, to an associated one of the bit lines;
the test circuit being integrated in the ferroelectric memory component and having a test mode;
the sense amplifiers being in a state selected from the group consisting of a non-activated state and a disconnected state during the test mode; and
the test circuit, when in the test mode, outputting, via the analog amplifiers, analog signals from the ferroelectric memory cells and present on the bit lines connected to the ferroelectric memory cells to a point outside the ferroelectric memory component for an external evaluation of the analog signals.
With the objects of the invention in view there is also provided, a circuit configuration, including:
a ferroelectric memory component having a plurality of ferroelectric memory cells, bit lines and sense amplifiers connected to the bit lines;
a test circuit including an analog amplifier provided for the bit lines, the analog amplifier having an input;
a switching device connected to the input of the analog amplifier and configured to switch analog signals from the bit lines successively to the input of the analog amplifier;
the test circuit being integrated in the ferroelectric memory component and having a test mode;
the sense amplifiers being in a state selected from the group consisting of a non-activated state and a disconnected state during the test mode; and
the test circuit, when in the test mode, outputting, via the analog amplifier, analog signals from the ferroelectric memory cells and present on the bit lines connected to the ferroelectric memory cells to a point outside the ferroelectric memory component for an external evaluation of the analog signals.
In other words, the object of the invention is achieved by a combination of a test circuit with a ferroelectric memory component having a plurality of ferroelectric memory cells, bit lines and sense amplifiers connected to the bit lines, the test circuit being integrated in the ferroelectric memory component, wherein the test circuit has either in each case an analog amplifier connected, on the input side, to an associated bit line of the ferroelectric memory module, or, the test circuit has an individual analog amplifier for a plurality of bit lines and a first switching device, in order to connect analog signals from a plurality of bit lines successively to an input of the one analog amplifier, and wherein the test circuit, in a test mode with non-activated or disconnected sense amplifiers of the ferroelectric memory module, outputs the analog signal values occurring on the bit lines from the ferroelectric memory cells connected to the bit lines via the analog amplifier or amplifiers to a point outside the memory module, in order to feed these analog signals to a downstream evaluation device.
Thus, according to the invention, a test circuit having one or more analog amplifiers and, in the case of one analog amplifier, a first switching device is accordingly integrated into the ferroelectric memory component, which test circuit, in a test mode with non-activated or disconnected amplifiers, is set up for the analog outputting of bit line signals from the memory component to the outside. Thus, by way of example, analog signals can be tapped off from one or more test pads of the test circuit and be fed for evaluation to a measuring unit which is connected downstream and is connected to the test pad. The output signal to be tapped off at the test pad should represent an unambiguous function of the bit line signal. By way of example it is possible to use one or more analog amplifiers in order to output measurement signals with high resolution. In one embodiment, it is possible to use a separate analog amplifier for each bit line, or alternatively, for example with the aid of a switching device, one analog amplifier for a plurality of bit lines. In the test mode, the sense amplifiers which are used during normal operation are either not activated or are electrically isolated from the bit lines by switching elements.
According to another feature of the invention, an output of the test circuit or the output or the outputs of the analog amplifier or amplifiers is or are connected to a test pad of the memory module.
According to yet another feature of the invention, a second switching device is provided at the output of the analog test circuit or of the analog amplifier or amplifiers, with which the analog output signal can be switched from this output or these outputs to an output terminal or a test pad of the memory module.
According to another feature of the invention, the test circuit or the analog amplifier or amplifiers is or are set up in such a way that the analog bit line signals to be output can be output with high resolution and without influencing the bit line potentials at the output terminal or test pad.
The test circuit according to the invention can be fabricated at the same time as the circuit of the memory component in a CMOS basic process without additional process steps.
The test circuit proposed according to the invention has, in particular, the following advantages:
lower test complexity, shorter test time, lower data processing complexity,
single-cell evaluation possible with little complexity;
complete analog information may be provided, for example including information about retention (in contrast to the previous solution),
higher resolution, and
direct outputting of information without loss of information for example through fluctuations of the sense amplifiers.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a test circuit for the analog measurement of bit line signals of ferroelectric memory cells, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.